This invention relates generally to communication devices. More particularly, this invention relates to a programmable, completely digital intermediate frequency transceiver for use in communication systems.
Intermediate frequency transceivers have traditionally been implemented as analog devices. Increasingly, growing numbers of functions of intermediate frequency transceivers have been implemented with digital circuits. FIG. 1 illustrates in block diagram form a prior art completely digital intermediate frequency receiver 10, which is commonly referred to as a bandpass digitized receiver. Receiver 10 includes a Flash Analog-to-Digital converter (A/D) 12, which directly digitizes the incoming intermediate frequency input signal. Flash A/D 12 offers the advantages of a large sampling bandwidth and a high spurious-free dynamic range; however these advantages are offset by significant disadvantages. First, Flash A/D 12 is typically realized using a bi-polar CMOS process, rather than the standard digital CMOS processes used to realize Digital Mixer 13 and Digital Filter 14. This difference in CMOS processes prevents realization of Receiver 10 on a single substrate. Second, the amplitude resolution of Flash A/D 12 is limited to about eight bits. Receiver 10 as a whole suffers from another disadvantage. Receiver 10 is designed about specific, fixed frequencies, including intermediate frequency, FIF, sampling frequency, Fs, and down conversion frequency, FM. Any change in the value of any of these quantities requires a redesign.
Other types of A/Ds have not been deemed suitable alternatives to a Flash A/D in a completely digital IF Transceiver. Sigma-delta modulators are used as A/Ds in audio applications; however, their frequency range is inadequate for use in radio applications. Briefly described, delta modulation is an analog-to-digital conversion process where the output digital code represents the change, or slope, of the analog input signal, rather than the absolute value of the analog input signal. A sigma-delta converter is an oversampling analog-to-digital converter where the analog signal is sampled at rates much higher (e.g., 64 times) than the sampling rates that would be required with a Nyquist converter. Sigma-delta converters integrate the analog signal before performing delta modulation. The integral of the analog signal is encoded rather than the change in the analog signal, as is the case for traditional delta modulation.
The demand for completely digital IF receivers is mirrored by a demand for completely digital IF transmitters. FIG. 6 illustrates in block diagram form a prior art intermediate frequency transmitter 100, which includes Digital-to-Analog Converters (D/A) 104 and 106 and analog Mixer 108. D/A 104 converts the digital In-phase data (I) into an analog I signal, while D/A 106 converts the digital Quadrature data (Q) into an analog Q signal. Analog Mixer 108 mixes the analog I and Q signals using a clock signal FM to generate the IF output signal. Prior art transmitter 100 suffers from at least three disadvantages. First, transmitter 100 is implemented entirely with analog devices, achieving high performance is expensive. Second, because of its analog circuitry transmitter 100 cannot be realized as a monolithic CMOS device. Finally, transmitter 100 is designed about specific, fixed values of intermediate frequency, FIF, and up conversion frequency, FM. Any change in the value of either of these frequencies requires a redesign.
Thus, a need exists for a monolithic, programmable, completely digital intermediate frequency transceiver suited for application in a highly integrated, flexible, low-cost, low power device for communication applications.
The monolithic CMOS programmable digital intermediate frequency receiver of the present invention includes a programmable memory, a clock generator, a sigma delta converter, a digital downconverter, and a decimation filter network. The programmable memory receives and stores a first value representative of a programmable parameter k and a second value representative of programmable parameter N. Coupled to the programmable memory, the clock generator generates a first clock signal, a second clock signal and a third clock signal. The first clock signal has a first frequency, fl, the second clock signal has a second frequency approximately equal to fl/k and the third clock signal has a third frequency approximately equal to fl/N. The sigma delta converter samples an analog input signal having an intermediate frequency using the first clock signal to generate a first set of digital signals. The digital downconverter mixes down the first set of digital signals using the second clock signal to generate a second set of digital signals. Finally, the decimation filter network filters the second set of digital signals using the third clock signal to generate a third set of digital signals.
The invention may also be realized as a completely digital, programmable monolithic CMOS IF Transceiver. The completely digital architecture achieves intermediate frequency up-conversion and down-conversion. A combination sigma-delta architecture and polyphase filter is used to achieve the up-conversion and down-conversion.
The invention allows the replacement of expensive analog components with lower-cost CMOS digital circuits. The invention facilitates the use of a single architecture across a wide variety of intermediate frequencies and channel bandwidths. The completely digital path ensures a linear transmit and receive path.